Monday, February 22, 2010

Instrumenting the AST

Here is the place for you to leave comments on "Instrumenting the AST" wherein I describe an way to modify the AST for Python code in order to insert new code for things like line and branch tracing and ways to add tests which aren't otherwise easily possible.

3 comments:

Paddy3118 said...

In chip design, it costs a lot to fab an ASIC so their is a ready market for Coverage tools for the Verilog and VHDL languages used in chip design.

Coverage tools for these languages have evolved ways to display the expression coveraage results you speak of in your "x = a or b or c" example; an can also handle multiple expressions on a line etc.

The problem is that the tools are proprietary, but I have found one online source of documentation on what we can do:

http://www10.edacafe.com/book/parse_book.php?article=transeda%2Fch-06.html

Maybe reading that will help.

- Paddy.

Loki said...

Great tool to visualize your ast tree: http://svn.python.org/projects/python/trunk/Demo/parser/unparse.py

vipin said...

I wanted to solve this problem (http://stackoverflow.com/questions/41977636/how-to-port-slots-from-python-2-to-3)

using ast module but it seems nodes in ast tree don't have links to parent nodes. I think there still might be a way to build such a tree by ourselves but it would be nice to have a configuration such that ast tree has links and flexibility to move around the nodes in the tree.