Monday, February 22, 2010
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About Me
- Andrew Dalke
- I am an American living in Göteborg, Sweden. I make my living writing software for computational chemistry and biology, usually in Python.
5 comments:
In chip design, it costs a lot to fab an ASIC so their is a ready market for Coverage tools for the Verilog and VHDL languages used in chip design.
Coverage tools for these languages have evolved ways to display the expression coveraage results you speak of in your "x = a or b or c" example; an can also handle multiple expressions on a line etc.
The problem is that the tools are proprietary, but I have found one online source of documentation on what we can do:
http://www10.edacafe.com/book/parse_book.php?article=transeda%2Fch-06.html
Maybe reading that will help.
- Paddy.
Great tool to visualize your ast tree: http://svn.python.org/projects/python/trunk/Demo/parser/unparse.py
I wanted to solve this problem (http://stackoverflow.com/questions/41977636/how-to-port-slots-from-python-2-to-3)
using ast module but it seems nodes in ast tree don't have links to parent nodes. I think there still might be a way to build such a tree by ourselves but it would be nice to have a configuration such that ast tree has links and flexibility to move around the nodes in the tree.
Hi. "Manual Tree Walking Is Better Than Tree Grammars" link in your text is dead. FYI. Thanks.
It's a nearly 9 year old blog post. Thing change and I've long given up caring to maintain old posts. Stick the title into a web search engine to find the newest location, or use archive.org.
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